1. Field of the Invention
The present invention relates in general to a high speed interface device, and in particular to an improved high speed interface type device which can improve data I/O efficiency by increasing data output in one period in an SDRAM, by four times, and which can provide a bus structure for enabling more precise synchronization of a data and a clock during high speed operation.
2. General Background and Related Art
In general, a high speed DRAM such as a direct Rambus DRAM or sync link DRAM has a higher data processing speed than a conventional DRAM. Accordingly, the direct Rambus DRAM or sync link DRAM must be used in consideration of a data processing speed of peripheral systems. It is thus difficult to use a direct Rambus DRAM or sync link DRAM in all memory products. Therefore, it is required to develop a high speed DRAM by gradually improving the existing DRAM. Recently, many companies have attempted to design a double data rate (DDR) SDRAM. The DDR SDRAM also has been actively discussed in the JECEC and the like. In the DDR SDRAM, a data or command is synchronized in a rising edge and falling edge of a clock (100 MHz). That is to say, a 2 bit data is transmitted to a clock having one period in each DQ pad. Accordingly, the 100 MHz clock can obtain a data rate corresponding to a 200 MHz clock. As a result, an external 100 MHz clock is applied, thereby generating a 200 MHz clock. In this case, when the clock duty is exactly 50%, frequency can be doubled.
FIG. 1 (Prior Art) is a block diagram of a system bus structure of a conventional interface type device. The conventional interface type device includes a controller 100 and a plurality of DRAMs 200˜200n controlled by the controller 100.
FIG. 2 (Prior Art) is a timing diagram illustrating data I/O during read and write operations in the conventional interface type device. The operation of the conventional interface type device will now be explained with reference to FIG. 2 (Prior Art).
During a write operation, the controller 100 transmits a clock signal CCLK, and a command signal, an address signal and a write data signal synchronized with the clock signal CCLK to the DRAMs 200˜200n. During a read operation, the controller 100 receives read data signals Data synchronized with data strobe signals DQS0, DQS1 from the DRAMs 200˜200n. 
In addition, in the write operation, the DRAMs 200˜200n receive the clock signal CCLK, and the command signal, the address signal and the write data signal synchronized with the clock signal CCLK from the controller 100. According to the input clock signal CCLK, the DRAMs 200˜200n generate a first internal clock signal locked through an internal DLL circuit (not shown), and a second internal clock signal having a 90° phase difference from the first internal clock signal. Thereafter, the DRAMs 200˜200n receive a 2 bit write data in one period of the clock signal CCLK, and store the data in cells of a memory cell array according to the first and second internal clock signals.
During a read operation, the DRAMs 200˜200n synchronize the data Data from the memory array with the first and second internal clock signals from the internal DLL circuit, and synchronize a 2 bit read data with the data strobe signals DQS0, DQS1 in one period of the clock signal CCLK, thereby outputting the resultant data to the controller 100.
As described above, in the conventional interface type device, the 2 bit write data synchronized with the clock signal CCLK is transmitted from the controller 100 to the DRAMs 200˜200n during the write operation, and the 2 bit read data Data synchronized with the data strobe signals DQS0, DQS1 is transmitted from the DRAMs 200˜200n to the controller 100 during the read operation.
When the controller 100 transmits the write data to the respective DRAMs 200˜200n during the write operation, the conventional interface type device requires a write input driver circuit for synchronizing the write data with the clock signal CCLK, and transmitting the resultant data. In the case that the DRAMs 200˜200n transmit the read data to the controller 100 during the read operation, the conventional interface type device requires a read output driver circuit for synchronizing the read data with the data strobe signals DQS0, DQS1, and transmitting the resultant data. That is, the conventional interface type device requires the additional write input driver and read output driver in each DRAM, thereby occupying a large circuit area. Moreover, the driver circuits increase power consumption.